Modern switching hardware supports complex packets that stack multiple protocols such as multiprotocol label switching (MPLS), stacked virtual local area network (VLAN), and internet protocol (IP)-in-IP. In order to process a packet, hardware may classify each packet by comparing a key taken from the packet to a table of flow entries. Virtualization, tunneling. OpenFlow, and network address translation (NAT) applications may require a flow table of more than 100K entries, each of which can be 64 or more bytes. Some protocols requires that the classification process for a packet happen within a single clock cycle, with low latency and low power consumption.
Some memory architectures, such as content-addressable memory (CAM) may include a deterministic table structure for low latency classification, but may also consume much more power (e.g., ten times) and take up much more area (e.g., four times or more) than a random-access memory (RAM) of the same size. In some examples, hash tables may be used in a RAM architecture because of the limitations of a CAM architecture, but RAM architectures have limitations, such as an inability to fill a RAM architecture to capacity (e.g., only up to 60% capacity) due to collision and latency issues.